1. Field of the Invention
The present invention relates to semiconductor memory devices, and particularly to a semiconductor memory device including a latch type (cross-coupled type) sense amplifier circuit for sensing and amplifying the potential of a bit line pair. More particularly, the present invention relates to the structure of circuitry that drives a latch type sense amplifier.
2. Description of the Background Art
FIG. 1 shows a structure of a main part of a conventional semiconductor memory device disclosed in, for example, Japanese Patent Laying-Open No. 8-87887. Referring to FIG. 1, the semiconductor memory device includes two memory cell arrays mal and mar with a plurality of memory cells mc arranged in a matrix therein. A bit line bl is arranged corresponding to each column of memory cells mc. A word line wl is arranged corresponding to each row of memory cells mc. In FIG. 1, bit lines bl0 and bl1 in memory cell array mal and bit lines/bl0 and /bl1 in memory cell array mar are shown. The semiconductor memory device employs the open bit line configuration. A memory cell is arranged corresponding to the crossing of a bit line and a word line in each of memory cell arrays mal and mar. A plurality of memory cells mc are coupled to a corresponding bit line in a unit of a predetermined number of memory cells. In other words, a memory unit has a NAND type memory cell structure.
The semiconductor memory device further includes a select gate 5a connecting bit line bl0 or bl1 to a common bit line bl according to select signals st0 and st1, a select gate 5b connecting bit line /bl0 or /bl1 to a common bit line /bl according to select signals st0 and st1, an equalize circuit 6c equalizing common bit lines /bl and bl to an intermediate voltage level when active, a temporary storage register 7 to store the data on common bit lines bl and /bl temporarily, and a cross-coupled sense amplifier sa sensing, amplifying, and latching the signal potentials of common bit lines bl and /bl when made active. Cross-coupled sense amplifier sa includes p channel MOS transistors (insulated gate type field effect transistor) having the gates and drains cross-coupled, and n channel MOS transistors having the gates and drains cross-coupled. Common bit lines bl and /bl are coupled to internal data lines db and /db via a column select gate 8 that is rendered conductive according to a column select signal cs1.
One sense amplifier sa is provided per two bit line pairs of each of memory cell arrays mal and mar. Sense amplifier control circuit 1 is provided to drive a plurality of sense amplifiers sa in common.
Sense amplifier control circuit 1 includes a sense amplifier drive transistor 1a receiving a sense amplifier activation signal BSEP at its gate via an inverter 1b to be rendered conductive, for driving a sense amplifier drive signal BSAN on a sense amplifier drive line 4n to the level of a ground voltage, a sense amplifier drive transistor 1c rendered conductive when sense amplifier activation signal BSEP is active to drive a sense amplifier drive signal SAP on sense amplifier drive line 4p to the level of a power supply voltage VCC, an inverter 2a inverting sense amplifier activation signal BSEP, a NAND circuit 2b receiving an output signal of inverter 2a and a restore mode designating signal BRSTR, a sense amplifier drive transistor 3a receiving an output signal of NAND circuit 2b at its gate via an inverter 3b to be rendered conductive for driving sense amplifier drive line 4n to the level of the ground voltage, and a sense amplifier drive transistor 3c rendered conductive when output signal RBSEP of NAND gate 2b is at an L level to drive sense amplifier drive line 4p to the level of power supply voltage Vcc. Restore mode designating signal BRSTR specifies a mode of writing the data sensed and amplified by sense amplifier sa into the original memory cell.
The operation of the semiconductor memory device of FIG. 1 will be described with reference to a waveform diagram of FIG. 2.
One of memory cell arrays mal and mar has a word line driven to a selected state. The word lines are at a nonselected state in the other memory cell array. The memory unit includes four memory cells. Here, the selected memory unit has the data read out from the memory cell located closest to common bit line bl or /bl. More specifically, word lines wl0, wl1, wl2 and wl3 are sequentially selected when memory cell array mal is selected, as shown in FIG. 2. Upon selection of word line wl0, select signals st0 and st1 are driven to an active state alternately, whereby bit lines bl0 and bl1 are connected to common bit line bl alternately. Similarly, bit lines /bl0 and /bl1 are sequentially coupled to common bit line /b1.
When select signals st0 and st1 attain an inactive state, activation of sense amplifier sa is carried out. More specifically, sense amplifier activation signal BSEP attains an active state of an L level (logical low) in a read out mode. At this stage, restore mode designating signal BRSTR maintains an H level (logical high). Since inverter 2a and NAND circuit 2b operate as a buffer circuit, sense amplifier drive transistors 1a, 1c, 3a and 3c conduct, whereby sense amplifier drive signal SAP is driven to the level of power supply voltage Vcc and sense amplifier drive signal BSAN is driven to the level of ground voltage. In response, sense amplifier sa is rendered active. A small signal voltage transferred from bit line bl0 is sensed, amplified, and latched. The data sensed and amplified by sense amplifier sa is stored in temporary storage register 7. The operation of driving the sense amplifier and storing the data into temporary storage register 7 following activation of select signals st0 and st1 is also carried out for other word lines wl0-wl3. By activating sense amplifier sa only common bit lines bl and /bl coupled to sense amplifier sa when select signals st0 and st1 are rendered inactive, the load on sense amplifier sa is reduced to allow a high speed sensing operation.
Upon completion of reading out the data of memory cells on word lines wl0-wl3, a restore mode operation of rewriting the data into the original memory cells is carried out. In the restore mode operation, restore mode designating signal BRSTR attains an L level, and control signal RBSEP is fixed at an H level. Therefore, sense amplifier drive transistors 3a and 3c maintain the inactive state. Data are rewritten into memory cells in the sequence opposite to that of reading out data. The data stored in temporary storage register 7 is amplified by sense amplifier sa. The amplified data is written into the original memory cell through select gate 5a. Sense amplifier drive lines 4p and 4n are only driven by sense amplifier drive transistors 1c and 1a, and drivability therefor is smaller than that in data read out. After sense amplifier sa is rendered active, in response to sense amplifier activation signal BSEP, to change the voltage level of common bit lines bl and /bl, select signal st0 or st1 is driven, and the bit line is driven gently by the sense amplifier via select gate 5a. By reducing the drivability of sense amplifier sa in the rewrite (restore) operation mode, leakage current Icc during rewriting can be reduced. Generation of power supply noise can be suppressed and reduction in current consumption is realized.
The restore operation to memory cell mc is carried out by repeatedly rendering sense amplifier activation signal BSEP active/inactive a predetermined number of times according to a clock signal CKB. Upon completion of rewriting data into memory cell mc connected to word line wl3, rewriting data into memory cell mc connected to word line wl2 is then carried out. The rewriting operation into the memory cells connected to word lines wl1 and wl0 is sequentially carried out thereafter.
Clock signals CKA and CKB are generated to determine respective sense amplifier operation periods for the read out mode and restore mode. A basic clock signal TCK to activate the sense amplifier is generated by clock signals CKA and CKB.
The leakage current is reduced by setting the drivability of sense amplifier sa smaller in the restore operation. However, the time required for rewriting becomes longer than the time required for data reading since sense amplifier sa drives the bit lines in memory cell arrays mal and mar. Thus, there is a problem that the time for restore becomes longer.
The prior art document described above is directed to application of a NAND cell structure in which a memory unit has a plurality of memory cells connected in series. This prior art teaches that the prior art arrangement is applicable even if the memory unit includes only one memory cell as long as sense amplifier sa is isolated from a corresponding bit line during a sensing operation. However, the prior art is silent about how data is written in a single memory cell structure. The prior art only discloses reducing the drivability of the sense amplifier at a restore mode in a read out operation, and rewriting data retained in temporary storage register 7 to a memory cell through sense amplifier sa.
According to the structure of FIG. 1, two sense amplifier drive transistors must be provided for each of sense amplifier drive lines 4p and 4n. In order to speed up the data read out operation, sufficient drive current must be applied to sense amplifier sa to enhance the current driving capability of sense amplifier sa. However, when the sense amplifier drive transistor is arranged at each end of sense amplifier drive lines 4p and 4n in a structure where many sense amplifiers sa are provided as shown in FIG. 1, the interconnection line length of sense amplifier drive lines 4p and 4n will becomes longer. As a result, the drivability of a sense amplifier located at a remote position is degraded by the delay in transition of the drive signal caused by the line capacitance and line resistance, and by change in the power supply voltage for each sense amplifier according to the voltage distribution. Therefore, the speed of the read out operation cannot be improved (because the data read out time is determined depending upon the worst-case sense amplifier operation).
In order to eliminate the problem caused by the line capacitance and the line resistance in sense amplifier drive lines 4p and 4n, a sense amplifier drive transistor should be provided corresponding to each sense amplifier sa. However, two sense amplifier drive transistors must be provided in parallel between the sense amplifier power supply node and the power supply line for each sense amplifier (in order to speed up the restore operation). This means that four sense amplifier drive transistors must be arranged for one sense amplifier. Thus, there is a problem that the area of the sense amplifier arrangement region is increased significantly.
The sense amplifier located remote from the sense amplifier drive transistor in the structure of FIG. 1 has the amount of change of drivability thereof reduced in between a read out operation and a restore operation by the line resistance and line capacitance of the sense amplifier drive line. Thus, there is a problem that the read out operation cannot be carried out speedily, as well as a problem of suppressing speed up of the restore operation.
Where data is sequentially stored in the temporary storage register as in the prior art when external data is to be written into a memory cell, the sense amplifier must be rendered active/inactive for each data writing. Thus, there is a problem that data cannot be written sequentially at high speed.